I am currently a Ph.D candidate of the University of Rennes1, France. I received the M.S. degrees in Software Engineering from Harbin Institute of Technology(HIT) and Enterprise Computing & Engineering from and the University of Bordeaux1 in 2009. My research interests focus on high-level synthesis, application specific instruction processors and compilation optimization approaches.
Short Bio
Publications
International Journals
Chenglong Xiao, Emmanuel Casseau: An automated synthesis flow of custom instruction for extensible processors. Springer, Journal of Real-Time Image Processing, 2012 (Invited: Special Issue on Best Papers from DASIP 2011, Submitted to)
Chenglong Xiao, Emmanuel Casseau: Exact custom instruction enumeration for extensible processors. Elsivier, Integration, the VLSI journal , 2012 (Invited: Special Issue on Best Papers from ACM GLSVLSI 2011)
International Conferences
Chenglong Xiao, Emmanuel Casseau: Efficient maximal convex custom instruction enumeration for extensible processors. DASIP 2011, Tampere, Finland, 137-143
Chenglong Xiao, Emmanuel Casseau: Efficient custom instruction enumeration for extensible processors. IEEE ASAP 2011, Santa Monica, USA, 211-214
Chenglong Xiao, Emmanuel Casseau: An efficient algorithm for custom instruction enumeration. ACM GLSVLSI 2011, Lausanne, Switzerland, 187-192
National Workshop
Chenglong Xiao, Emmanuel Casseau: Pattern Extraction for Digital Design. Colloque GDR SOC-SIP 2010, Paris, France.
Contact
INRIA/IRISA - Equipe de Recherche CAIRN
BP 80518 - 6 Rue de Kérampont
22305, Lannion, France
Email: chenglong.xiao@irisa.fr