[1]
O. Sentieys.
Analyse et synthèse d’architectures en traitement du signal et
d’images : vers la conception d’architectures hétérogènes.
Université de Rennes I - ENSSAT, February 1993.
[2]
O. Sentieys.
Méthodologies de conception de circuits et systèmes enfouis :
application dans le domaine des télécommunications.
Habilitation à Diriger des Recherches Université de Rennes I - ENSSAT,
January 1999.
Journals
[3]
J.P. Diguet, D. Chillet and O. Sentieys.
A Framework for High-Level Estimations of Signal Processing
Implementations.
Journal of VLSI Systems for Signal, Image and Video Technology,
Volume 25, Number 3, July 2000.
[4]
H. Dubois, D. Chillet, J.L. Philippe and O. Sentieys.
Teaching Hardware/Software System Codesign using High-Level CAD tools : a case study in image synthesis.
IEEE Transactions on Education, Volume 43, Number 3, August 2000.
[5]
D. Chillet, J.P. Diguet, J.L. Philippe, and O. Sentieys.
Méthodologie de conception des unités mémoires appliquée au
traitement du signal temps réel.
Revue Technique et Science Informatique, Volume 16, 1997.
[6]
J.P. Diguet, O. Sentieys, J.L. Philippe, and E. Martin.
Mesures probabilistes de l’adéquation algorithme architecture.
Revue Traitement du Signal, Volume 14, 1997.
[7]
D. Chillet, J.L. Philippe, O. Sentieys, and H. Dubois.
Conception des unités mémoire pour des applications de traitement
du signal temps réel.
Revue Traitement du Signal, Volume 14, 1997.
[8]
J.L. Philippe, O. Sentieys, E. Martin, and H. Dubois.
Adéquation d’un algorithme à une architecture, application à la
transformée de fourier.
Revue Traitement du signal, 13(4):335–350, December
1996.
[9]
E. Martin, O. Sentieys, and J.L. Philippe.
Synthèse architecturale de cœur de processeurs de traitement du
signal.
Revue Techniques et Sciences Informatiques, 13(2), 1994.
[10]
O. Sentieys, E. Martin, H. Dubois, J.L. Philippe, and M. Corazza.
Application de l’outil espion pour l’analyse des architectures
multiprocesseurs au filtrage de kalman 2-d rapide.
Revue Traitement du Signal, 10(1), 1993.
[11]
P. Lutzler, O. Faraldi, P. Cosquer, M. Billon and O. Sentieys.
Chute du sujet agé : prototype de bracelet détecteur.
Revue de gérontologie, 2000.
Book Chapters
[12]
O. Sentieys, D. Chillet, J.P. Diguet, and J.L. Philippe.
Memory module selection for high level synthesis.
In IEEE Press, VLSI Signal Processing IX, 1996.
[13]
M. Auguin, M. Belhadj, J. Benzakki, C. Carriere, G. Durrieu, T. Gauthier, M. Israel,
P. Le Guernic, M. Lemaitre, E. Martin, P. Quinton, L. Rideau, F. Rousseau, and
O. Sentieys.
Framework and multi-formalism: The asar project.
In Electronic Design Automation Framework, Edited by F.J.Ramming
and F.R.Wagner, Chapman Hall, volume 4, pages 91–90, 1995.
[14]
J.P. Diguet, O. Sentieys, J.L. Philippe, and E. Martin.
Probabilistic resource estimation for pipeline architecture.
In IEEE Press, VLSI Signal Processing VIII, 1995.
[15]
J.L. Philippe, O. Sentieys, J.P. Diguet, and E. Martin.
From digital signal processing specifications to layout, pages
307–313.
In New techniques in Logic and Architectural Synthesis, Chapman Hall, G. Saucier and A. Mignotte, 1995.
[16]
J.P. Diguet, O. Sentieys, E. Martin, and J.L. Philippe.
How to specify an algorithm in vlsi architectural synthesis ? a vocal
coding application.
In IEEE Press, VLSI Signal Processing VII, 1994.
[17]
O. Sentieys, E. Martin, and J.L. Philippe.
VLSI architectural synthesis for an acoustic echo cancelation
application.
In IEEE Press, VLSI Signal Processing VI,
edited by L. Eggermont and Ed Deprettere, 1993.
Patents
[18]
O. Sentieys, M.Billon, H.L’Her, and M.Valette.
Système d’apprentissage au tir, équipement pour fusil, cible et
procédé correspondant.
Brevet numéro 96.06779, Université de Rennes 1, 1996.
[19]
O. Sentieys, M.Billon, H.L’Her, and M.Valette.
Dispositif et procédé de détermination d’informations
physiologiques, et utilisation correspondante.
Brevet numéro 97-14113, Université de Rennes 1, 1997.
[20]
O. Sentieys, M.Billon, P. Cosquer, H.L’Her, and M.Valette.
Système de téléalarme intelligente.
Brevet numéro 00-05822, Université de Rennes 1, 2000.
International Conferences
[21]R. David, D. Chillet, S. Pillement, O. Sentieys,
A Dynamically Reconfigurable Architecture for Low-Power Multimedia
Terminals,
in 11th IFIP Int. Conference on VLSI and System On Chip,
December 2001.
[22]S. Pillement, O. Sentieys, D. Chillet, E. Casseau,
P. Coussy, E.Martin, G. Savaton, S. Roux,
Design and synthesis of behavioral level virtual components,
in 11th IFIP Int. Conference on VLSI and System On Chip,
December 2001.
[23]
J.G. Cousin, M. Denoual, D. Saillé, O. Sentieys.
Fast ASIP synthesis and power estimation for DSP applications.
In IEEE Symposium on signal processing systems SIPS’2000 , Lafayette, LA, pp 591-600, 2000.
[25]
M.Denoual, D.Saillé, J.G.Cousin and O.Sentieys.
Fast Power Estimation at the Architectural Level.
In International Conference on Design of Circuits and Integrated Systems DCIS’2000, Montpellier, pp 88-93, 21-24 November, 2000.
[26]
J-G. Cousin, O. Sentieys and D. Chillet.
Multi-algorithm ASIP Synthesis and Power Estimation for DSP Applications.
In IEEE International Symposium on circuits and
systems ISCAS’2000, Geneva, SW, may 28 - 31, 2000.
[27]
M. Denoual, D. Saillé and O. Sentieys.
PowerCheck : an Architectural-Level Power Estimation,
Workshop on Multi-Architecture Low-Power Design (MALOPD),
Moscou, September, 1999.
[28]
O. J. Dedou, D. Chillet, and O. Sentieys.
Behavioral Synthesis of Aynchronous Systems: a Methodology.
In IEEE International Symposium on circuits and
systems ISCAS’99, Orlando, USA, may 30 - june 2 1999.
[29]
D. Chillet, O. Sentieys, and M. Corazza.
Memory unit design for real time dsp applications.
In IEEE Great Lakes Symposium on VLSI GLSV’99, Ann
Arbor, Michigan, USA, March 1999.
[30]
J-G. Cousin, D. Chillet, and O. Sentieys.
ASIP Design and Power Estimation for DSP Applications.
In Sophia Antipolis Conference on Microelectronics. SAME’98,
October 1998.
[31]
O.J. Dedou, D. Chillet, and O. Sentieys.
Asynchronous Timing Model for High Level Synthesis for DSP
Applications.
In European Signal Processing IX: Theories and applications,
volume 1, pages 475–478. EUSIPCO-98, September 1998.
[32]
B. Meziane, M. Billon, O. Sentieys, and M. Corazza.
Performance of an ambulatory system in function-parameter analysis
and sleep characterization.
In 14th congress on sleep research, also in Journal of sleep
research Vol 7, sup 2, Madrid, Septembre 1998.
[33]
B. Meziane, M. Billon, O. Sentieys, and M. Corazza.
Heart rate and respiratory regulation during normal sleep:
investigation by spectral analysis and comparison with EEG recordings.
In VIII Mediterranean conference on medical and biological
engineering and computing medicon’98, Cyprus, June 1998.
[34]
S.J. Piestrak, F. Pedron, and O. Sentieys.
VLSI implementation ans complexity comparison of residue generators
modulo 3.
In European Signal Processing Conference EUSIPCO-98, Rhodos, Greece,
Septembre 1998.
[35]
J.Ph. Diguet, O. Sentieys, D. Chillet, and J.L. Philippe.
VLSI high level synthesis of fast exact least mean square
algorithms.
In ICASSP’97, 34th IEEE International Conference on Acoustic
Speech, and Signal Processing, Munich, Germany, April 1997.
[36]
S. Gailhard, O. Sentieys, N. Julien, and E. Martin.
Area/time/power space exploration in module selection for dsp high
level synthesis.
In PATMOS’97, Louvain la Neuve, September 1997.
[37]
J.L. Philippe, D. Chillet, O. Sentieys, and J.P. Diguet.
Memory aspects in signal processing and hls tool : Some results.
In European Signal Processing Conference, Trieste, Itaky,
September 1996.
[38]
O. Sentieys, D. Chillet, J.P. Diguet, and J.L. Philippe.
Memory module selection for high level synthesis.
In IEEE Workshop on VLSI Signal Processing, San Fransisco, USA,
30 octobre - 1 novembre 1996.
[39]
O. Sentieys, J.P. Diguet, J.L. Philippe, and E. Martin.
Hardware module selection for real time pipeline architectures using
probabilistic cost estimation.
In IEEE ASIC conference, Rochester, USA, September 1996.
[40]
J.P. Diguet, O. Sentieys, J.L. Philippe, and E. Martin.
Probabilistic resource estimation for pipeline architecture.
In T.Nishitani and K.Parhi, editors, IEEE Workshop on VLSI
Signal Processing, volume IEEE Press, pages 217–226, Osaka, Japon, November
1995.
[41]
O. Sentieys, J.P. Diguet, and J.L. Philippe.
Gaut : a high level synthesis tool dedicated to real time processing
application.
In University booth, EURO DAC, Brighton, September 1995.
[42]
P. Aubry, M. Auguin, M. Belhadj, J. Benzakki, C. Carriere, G. Durrieu, T. Gauthier,
M. Israel, P. Le Guernic, M. Lemaitre, E. Martin, P. Quinton, L. Rideau,
F. Rousseau, and O. Sentieys.
Framework and multi-formalism: the asar project.
In 4eme international IFIP conference on Electronic Design
Automation Frameworks, Gramado, Bresil, November 1994.
[43]
M. Auguin, M. Belhadj, J. Benzakki, C. Carriere, G. Durrieu, T. Gauthier, M. Israel,
P. Le Guernic, M. Lemaitre, E. Martin, P. Quinton, L. Rideau, F. Rousseau, and
O. Sentieys.
Towards a multi-formalism framework for architectural synthesis: the
asra project.
In 3eme international Workshop on hardware - software Codesign
Code/Cashe’94, Grenoble, 1994.
[44]
J.P. Diguet, O. Sentieys, E. Martin, and J.L. Philippe.
How to specify an algorithm in VLSI architectural synthesis ? a vocal
coding application.
In IEEE Workshop on VLSI Signal Processing, La Jolla,
Californie, October 1994.
[45]
J.L. Philippe, E. Martin, and O. Sentieys.
Adequacy architecture algorithm, an experiment in signal processing
by using fpga.
In VHDL Forum Spring’94, Tremezzo, Italy, 1994.
[46]
J.L. Philippe, O. Sentieys, J.P. Diguet, and E. Martin.
High level synthesis and layout issues: some results in digital
signal processing.
In IFIP Workshop on logic and architecture synthesis, Grenoble,
December 1994.
[47]
E. Martin, O. Sentieys, and J.L. Philippe.
Adaptative filtering algorithms in acoustic echo cancellation :
architecture complexity evaluation.
In Third international Workshop on Acoustic Echo Control,
Plestin les grèves, September 1993.
[48]
E. Martin, O. Sentieys, H. Dubois, and J.L. Philippe.
Gaut: an architectural synthesis tool for dedicated signal
processors.
In IEEE/ACM European Design Automation Conference EURO-DAC’93, pages 20–24, Hambourg, September
1993.
[49]
J.L. Philippe, E. Martin, and O. Sentieys.
Prototyping DSP using VHDL and CAD architectural tool.
In Spring’93, Insbruck, Austria, March 1993.
[50]
O. Sentieys, E. Martin, and J.L. Philippe.
VLSI architectural synthesis for an acoustic echo cancelation
application.
In IEEE Workshop on VLSI Signal Processing, Veldhoven,
Hollande, October 1993.
[51]
O. Sentieys, H. Dubois, J.L. Philippe, and E. Martin.
A methodology approach to configure architectures applied to an mimd
transputer based machine for image and signal processing.
In COST 229 Workshop on parallel computing, March 1992.