“Top Picks in VLSI Test and Reliability” is a workshop that collects and presents the most impactful publications in the past 6 years in the areas of VLSI test and reliability.
For this first inaugural edition of the workshop, all articles in conferences and journals published from 2017 until the submission deadline are eligible.
We accept self-nominations by authors in the form of a 2-page letter. On the first page, the authors should summarize the key ideas and contributions of the publication, and, on a second page, the description of the influence on ongoing research in the field and the potential of making a positive impact for the long term in the microelectronics industry.
Submitted publications will be reviewed by a committee of renowned experts in the field and will be shortlisted. An author of each shortlisted publication is required to attend the workshop in-person to present the publication, showcasing its influence and impact. The same committee (or a subset of it) will be also present at the workshop to select a final list of Top Picks which will be then invited for submission to an IEEE Design & Test special issue. The submission should not repeat or reword the original publication. It should be an extended version with new material. Alternatively it can be a de novo review or tutorial article on the general topic of the original publication. It may have an author list that is different compared to the original publication.
"Top Picks in VLSI Test and Reliability” will take place in conjunction with the 2023 IEEE International Test Conference.