(All times in PDT)

Thursday October 12^th

4:00 PM – 4:10 PM : Opening session

J. Athavale (Synopsys, USA)

H.-G. Stratigopoulos (Sorbonne Université, CNRS, LIP6, France)

4:10 PM – 5:00 PM : Keynote

Addressing Emerging Fault Modes with Testing and Reliability

S. Gurumurthy (AMD, USA)

5:00 PM – 6:30 PM : Session 1

Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications

G. Li (University of Iowa, USA), S. K. S. Hari (NVIDIA, USA), M. Sullivan (NVIDIA, USA), T. Tsai (NVIDIA, USA), K. Pattabiraman (The University of British Columbia, Canada), J. Emer (NVIDIA, USA), and S. W. Keckler (NVIDIA, USA)

Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

J. J. Zhang (Arizona State University, USA), T. Gu (New York University, USA), K. Basu (The University of Texas at Dallas, USA) and S. Garg (New York University, USA)

Analyzing and Increasing the Reliability of Convolutional Neural Networks on GPUs

F. F. dos Santos (INRIA, France), P. F. Pimenta (Federal University of Rio Grande do Sul, Brazil), C. Lunardi (Federal University of Rio Grande do Sul, Brazil), L. Draghetti (Federal University of Rio Grande do Sul, Brazil), L. Carro (Federal University of Rio Grande do Sul, Brazil), D. Kaeli (Northeastern University, USA), and Paolo Rech (Universtiy of Trento, Italy)

7:00 PM – 9:00 PM: Welcome Reception

 

Friday October 13^th

8:30 AM – 10:00 AM : Session 2

A Reliability Analysis of a Deep Neural Network

A. Bosio (École Centrale de Lyon, INL, France), P. Bernardi (Politecnico di Torino, Italy), A. Ruospo (Politecnico di Torino, Italy), and E. Sanchez (Politecnico di Torino, Italy)

Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

E. Ozen (University of California San Diego, USA) and A. Orailoglu (University of California San Diego, USA)

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime

W. Li (Chinese Academy of Sciences, China), Y. Wang (Chinese Academy of Sciences, China), H. Li (Chinese Academy of Sciences, China), and X. Li (Chinese Academy of Sciences, China)

10:00 AM – 10:30 AM :  Coffee Break

10:30 AM – 12:00 PM : Session 3

Device-Aware Test: A New Test Approach Towards DPPB Level

M. Fieback (TU Delft, The Netherlands), L. Wu (TU Delft, The Netherlands), G. C. Medeiros (TU Delft, The Netherlands), H. Aziza (Aix-Marseille Université, CNRS, IM2NP), S. Rao (IMEC, Belgium), E. J.  Marinissen (IMEC, Belgium), M. Taouil (TU Delft, The Netherlands), and S. Hamdioui (TU Delft, The Netherlands)

DFM-aware fault model and ATPG for intra-cell and inter-cell defects

A. Sinha (Intel, USA), S. Pandey (Intel, USA), A. Singhal (Intel, USA), A. Sanyal (Intel, USA), and A. Schmaltz (Intel, USA)

Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs

W. Dobbelaere (ON Semiconductor, Belgium), F. Colle (ON Semiconductor, Belgium), A. Coyette (ON Semiconductor, Belgium), R. Vanhooren (ON Semiconductor, Belgium), N. Xama (KU Leuven, Belgium), J. Gomez (KU Leuven, Belgium), G. Gielen (KU Leuven, Belgium)

12:00 PM – 1:00 PM : Lunch

1:00 PM – 2:30 PM : Session 4

Understanding and Mitigating Hardware Failures in Deep Learning Training Systems

Y. He (University of Chicago, USA), M. Hutton (Google, USA), S. Chan (Google, USA), R. De Gruijl (Google, USA), R. Govindaraju (Google, USA), N. Patil (Google, USA), and Y. Li (University of Chicago, USA)

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

E. Cheng (Stanford University, USA), S. Mirkhani (Meta, USA), L. G. Szafaryn (Intel, USA), C.-Y. Cher (Graphen Inc., USA), H. Cho (Sungkyunkwan University, South Korea), K. Skadron (University of Virginia, USA), M. R. Stan (University of Virginia, USA), K. Lilja (Robust Chip Inc., USA), J. A. Abraham (University of Texas at Austin, USA), P. Bose (IBM T. J. Watson Research Center, USA), and S. Mitra (Stanford University, USA)

Characterizing and Mitigating Soft Errors in GPU DRAM

M. B. Sullivan (NVIDIA, USA), N. R. Saxena (NVIDIA, USA), M. O’Connor (NVIDIA, USA), D. Lee (NVIDIA, USA), P. Racunas (NVIDIA, USA), S. Hukerikar (NVIDIA, USA), T. Tsai (NVIDIA, USA), S. K. S. Hari (NVIDIA, USA), and S. W. Keckler (NVIDIA, USA)

2:30 PM – 2:45 PM : Short Break

2:45 PM – 3:45 PM : Panel

Trends, Challenges, and Perspectives in VLSI Test and Reliability

Panelists: A. Singh (Auburn University, USA), S. Sunter (Siemens, Canada), M. Tahoori (Karlsruhe Institute of Technology, Germany), Y. Zorian (Synopsys, USA)

3:45 PM – 4:00 PM : Closing session

J. Athavale (Synopsys, USA)

H.-G. Stratigopoulos (Sorbonne Université, CNRS, LIP6, France)