[1] S. Pillement, O. Sentieys, and R. David. DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency. EURASIP Journal on Embedded Systems (JES), pages 1-13, 2008. Article ID 562326, 13 pages. [ bib | .pdf ]
[2] D. Menard, R. Rocher, and O. Sentieys. Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems. IEEE Transactions on Circuits and Systems I: Regular Papers,, 55(10):3197-3208, November 2008. [ bib | DOI | .pdf ]
[3] D. Menard, R. Serizel, R. Rocher, and O. Sentieys. Accuracy Constraint Determination in Fixed-Point System Design. EURASIP Journal on Embedded Systems, 2008:12, 2008. [ bib | DOI | .html | .pdf ]
[4] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. High-level Interconnect Delay and Power Estimation. Journal of Low Power Electronics (JOLPE), 4(1):21-33, 2008. [ bib | .pdf ]
[5] D. Chillet, R. David, E. Grace, and O. Sentieys. Structure mémoire reconfigurable. vers une structure de stockage faible consommation. RSTI - Technique et Science Informatiques, 27(1-2):183 - 204, February 2008. [ bib | http ]
[6] T. Hilaire, D. Menard, and O. Sentieys. Bit accurate roundoff noise analysis of fixed-point linear controllers. In IEEE International Conference on Computer-Aided Control Systems (CACSD'08), pages 607-612, September 2008. [ bib | .pdf ]
[7] H.-N. Nguyen, D. Menard, R. Rocher, and O. Sentieys. Energy reduction in wireless system by dynamic adaptation of the ?xed-point speci?cation. In Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , pages 132-139, Bruxelles, Belgium, November 2008. [ bib | .pdf ]
[8] J. Lallet, S. Pillement, and O. Sentieys. Efficient dynamic reconfiguration for multi-context embedded fpga. In Proceedings of the 21st annual symposium on Integrated circuits and system design, SBCCI'08, pages 210-215, New York, NY, USA, 2008. ACM. [ bib | DOI | .pdf ]
[9] S. Pillement, JM. Philippe, and O. Sentieys. A new approach of coding to improve speed and noise tolerance of on-chip busses. In International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pages 1-6, Tozeur, Tunisia, March 2008. [ bib | DOI | .pdf ]
[10] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. New directions in interconnect performance optimization. In International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pages 1-6, Tozeur, Tunisia, March 2008. [ bib | DOI | .pdf ]
[11] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. Novel cross-transition elimination technique improving delay and power consumption for on-chip buses. In International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 359-368, Lisbon, Portugal, March 2008. [ bib | DOI | .pdf ]
[12] T.D. Nguyen, O. Berder, and O. Sentieys. Efficient space time combination technique for unsynchronized cooperative miso transmission. In IEEE 67th Vehicular Technology Conference (VTC Spring 2008), pages 629-633, Marina Bay, Singapore, May 2008. [ bib | DOI | .pdf ]
[13] T.D. Nguyen, O. Berder, and O. Sentieys. Impact of transmission synchronization error and cooperative reception techniques on the performance of cooperative mimo systems. In Proceedings of IEEE International Conference on Communications (ICC'08), pages 4601-4605, Beijing, China, May 2008. [ bib | DOI | .pdf ]
[14] O. Berder, P. Quémerais, O. Sentieys, J. Astier, T.D. Nguyen, J. Ménard, G. Le Mestre, Y. Le Roux, Y. Kokar, G. Zaharia, R. Benzerga, X. Castel, M. Himdi, G. El Zein, S. Jegou, P. Cosquer, and M. Bernard. Cooperative communications between vehicles and intelligent road signs. In Proceedings of the 8th International Conference on ITS Telecommunications (ITST), pages 121 - 126, Phuket, Thailand, October 2008. [ bib | DOI ]
[15] D. Chillet, S. Pillement, and O. Sentieys. Reconfigurable artificial neural network model for task scheduling on reconfigurable soc. In Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , pages 92-99, Bruxelles, Belgium, November 2008. [ bib ]
[16] E. Grace, R. David, D. Chillet, and O. Sentieys. Morea: A memory-oriented reconfigurable embedded architecture. In Workshop on Design and Architectures for Signal and Image Processing (DASIP 2008) , pages 124-131, Bruxelles, Belgium, November 2008. [ bib ]
[17] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. Interconnect Explorer: a High-Level Estimation Tool for On-Chip Interconnects. In Sophia Antipolis MicroElectronics Forum (SAME 2008), Nice, France, October 2008. University Booth. [ bib | .pdf ]
[18] A. Courtay, O. Sentieys, J. Laurent, and N. Julien. Procédé et dispositif de codage, système électronique et support d'enregistrement associés, March 2008. Patent, Reference BFF 08P0103/HC. [ bib | .pdf ]

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