Track 2 - Most impactful keynotes and invited presentations from the past six years
System-Level Test, a Decade of Progress, where to for the Next Decade
Harry Chen, Mediatek Inc.
Abstract: The past decade has witnessed the expanding role of system-level test (SLT) in ensuring the quality and reliability of electronic products and systems. The trend is expected to continue, but with the manner of SLT conduct undergoing significant transformations as system complexity keeps rising. The talk will cover the evolution of SLT, its driving forces, connection to silent data corruption (SDC), and related research efforts in SLT DFT automation. We end with speculations about SLT trajectory as escalating demands in computing and energy efficiency propel drastic changes in future systems development.
Bio: Harry Chen holds the position of IC Testing Scientist at MediaTek investigating advanced design and test methodologies through academic collaborations. He actively participates in numerous conferences serving on technical program committees, publishing papers, and giving talks. Outside of MediaTek, he has served as co-chair of VLSI-TSA DAT Subcommittee, co-chair of SEMI Taiwan Testing Committee, and leads the SLT section of IEEE Heterogeneous Integration Roadmap (HIR) Test TWG. Prior to MediaTek, Harry worked at Analog Devices on mobile SoC integration, and at Cadence Design on IC test automation tools. He has EE degrees from MIT and Stanford University.
What is beyond AI? Societal opportunities and electronic design automation
Valeria Bertacco, University of Michigan
Abstract: The success of specialized hardware in enabling ML acceleration has been nothing short of remarkable. Today, neural network accelerators have matured into industrial-strength products. But there is more to computing than meets the neural network. To address the future needs of computing, a few pressing challenges must be urgently addressed, and the hardware community is critical in clearing the path to that future. In this talk, I will focus on those key challenges, including the skyrocketing computing demands of AI, its environmental sustainability, and critical features for next-generation AI as it seeps into an increasing number of human-centered domains. Along with those, I will outline new opportunities that the related solutions offer to the testing community.
Bio: Valeria Bertacco is the Mary Lou Dorf Collegiate Professor of Computer Science and Engineering, and Arthur F. Thurnau Professor of Engineering at the University of Michigan. Her research interests are in the area of computer system design. Throughout her career, she has contributed novel solutions in design validation and reliability, hardware-security assurance, and the design of specialized architectures for graph algorithms and machine learning. From 2018 to 2023, Prof. Bertacco was the Director of the Applications Driving Architectures (ADA) Research Center, funded by a consortium of semiconductor companies and the Defense Advanced Research Projects Agency (DARPA). The Center engaged the work of 10 US academic institutions and over 130 Ph.D. student researchers. Currently, she leads the MAVERIC collaborative, the University of Michigan’s initiative to advance semiconductor research and education. At Michigan, she also serves as the Vice Provost for Engaged Learning, supporting all international partnerships and co-curricular engagements. She received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. Prof. Bertacco joined the University of Michigan in 2003, after working as a research engineer for Systems Science Inc., and Synopsys.
Paradigm Shift: Structural Approaches to Analog and RF Test
Sule Ozev, Arizona State University
Abstract: TBA
Bio: Professor Sule Ozev received her doctorate from University of California San Diego's Computer Science and Engineering Department in 2002. That same year, she joined Duke University's Electrical and Computer Engineering Department as an assistant professor. She worked on testing mixed-signal and radiofrequency circuits, built-in-self test techniques, analysis and mitigation of process variations, defect-tolerant microprocessor systems, and on-line, and off-line testing of microfluidic devices. In August 2008, she joined Arizona State University's Electrical Engineering Department (now School of Electrical, Computer and Energy Engineering) as an associate professor, continuing on the same line of research. She received National Science Foundation (NSF) CAREER award in 2006, and various other awards from NSF, SRC, NASA and IBM. She has published more than 100 conference and journal papers and holds one U.S. patent.
Techniques for Reliability in Edge-AI Chips
Maksim Jenihhin, Tallin University of Technology (TalTech)
Abstract: Artificial Intelligence applications benefit from the seamless integration of cloud and edge computing, keeping the cloud to train complex AI models, and using the edge for fast and efficient real-time inferencing. The latter establishes the Edge AI concept and sets new reliability requirements for the backbone hardware chips backing safety- and mission-critical applications. The main research and engineering challenges for edge-AI chips reliability stem from the limited computing and energy resources of the edge devices. The talk discusses techniques for soft-error and lifetime reliability assessment and enhancement for Deep Learning accelerators. It advocates the role of approximate computing and looks into specifics of the systolic-array-, data-flow-based and industry-grade accelerator architectures for ASICs and FPGAs.
Bio: Maksim Jenihhin is a tenured associate professor of computing systems reliability and head of the research group “Trustworthy and Efficient Computing Hardware (TECH)” at the Tallinn University of Technology, Estonia. He received his PhD degree in Computer Engineering from the same university in 2008. His research interests include reliable and efficient hardware for AI acceleration, methodologies and EDA tools for hardware design, verification and security, as well as nanoelectronics reliability and manufacturing test topics. He has published more than 180 research papers, supervised several PhD students and postdocs and served on executive and program committees for numerous IEEE conferences (DATE, ETS, DDECS, EWDTS, VLSI-SoC, LATS, NorCAS, etc.). Prof. Jenihhin coordinates European collaborative research projects HORIZON MSCA DN “TIRAMISU” (2024), HORIZON TWINN “TAICHIP” (2024) and national ones about energy efficiency and reliability of edge-AI chips and cross-layer self-health awareness of autonomous systems.