On the need to rethink silicon test to reduce SDE and improve reliability

Sreejit Chakravarty, Distinguished Engineer and IEEE Fellow, Ampere Computing, Santa Clara, CA

Abstract: High volume manufacturing tests of silicon devices have relied primarily on structural tests like SCAN, memory BIST, and IO BIST. Structural test gaps have been filled with instruction level functional tests. The same is carried over to infield testing to address reliability issues. This approach has not solved the silent data error (SDE) problem. It has also left gaps in addressing reliability issues. The primary purpose of this talk is to highlight the need to rethink our silicon test strategy and identify several gaps that must be filled. In this talk we will also discuss some potential solutions to fill the gaps.

Bio: Dr. Sreejit Chakravarty is an IEEE Fellow, a highly recognized Researcher, Inventor, and a Distinguished Engineering Leader, with extensive industry and academic experience.

He is currently a Distinguished Engineer at Ampere Computing, Santa Clara, CA, USA where he drives strategic initiatives for product quality. Prior to this he had over 25 years of industry experience as a Principal Engineer with Intel Corporation and Distinguished Engineer at LSI and AVAGO (now Broadcom). He started his career in academia as an Associate professor of Computer Science, at The State University of New York at Buffalo, where his work was funded by multiple National Science Foundation Grants.

He has architected innovative solutions across the entire silicon life cycle spanning Silicon Quality and Reliability (RAS, Functional Safety and Silent Data Errors); and subsequently drove them from concept to product intercept.

He has published 1 book, authored 145+ IEEE papers and has 23 issued US patents. He has served in various capacity at numerous IEEE conferences and delivered multiple keynote addresses, the latest being at the IEEE Asian Test Symposium, 2023. He has mentored research at several universities like Princeton, USC, UIUC, etc. For his professional work he has been recognized as an IEEE Fellow and SUNY Distinguished Alumni. He currently chairs the IEEE P3405 Work Group on Chip-Let Interconnect Test and Repair, which aims to standardize the test and repair of Chip-Let interconnects, and will lay the foundation to realize the Chip-Let revolution.