Combined Wordlength Optimization and High-Level Synthesis
We proposed a high-level synthesis methodology based on a generic fixed-point operator library Error noise propagation model is used to compute an closed-form expression of the accuracy as a function of the data wordlength.
- N. Hervé, D. Menard, and O. Sentieys. Data wordlength optimization for fpga synthesis. In Proceedings of the IEEE International Workshop on Signal Processing Systems, SIPS’05, pages 623-628, Athens, Grece, November 2005. [ pdf ]
- R. Rocher, D. Menard, N. Hervé, and O. Sentieys. Fixed-Point Configurable Hardware Components. EURASIP Journal on Embedded Systems (JES), 2006(1):Article ID 23197, 13 pages, 2006. [ pdf ]
Resource Cost Estimation in HLS
Estimating the cost and performance of the result of HLS without actually performing the synthesis is still an important issue in system design. In the BSS framework, we proposed both synthesis of dedicated VLSI circuits and cost, performance estimation. The latter can be used at different accuracy levels and takes account of both the processing unit — including operators, registers, interconnections — and memory units. Our estimation techniques include functional unit number bound calculation and probabilistic cost estimation.
- J.P. Diguet, D. Chillet and O. Sentieys. A Framework for High-Level Estimations of Signal Processing Implementations. Journal of VLSI Systems for Signal, Image and Video Technology, Volume 25, Number 3, July 2000. [ pdf ]
- 2.J.P. Diguet, O. Sentieys, J.L. Philippe, and E. Martin. Probabilistic resource estimation for pipeline architecture. In IEEE Press, VLSI Signal Processing VIII, 1995.
During my PhD thesis [sic], I worked on defining the GAUT HLS tool and programmed the first version of the tool. This tool is now widely used and still developed at Lab-Sticc. After that, I also worked on various aspects of HLS like resource selection and allocation, high-level cost and performance estimation, interfaces, HLS of asynchronous circuits, behavioral IP specification and web integration framework.
- E. Martin, O. Sentieys, H. Dubois, and J.L. Philippe. Gaut: an architectural synthesis tool for dedicated signal processors. In IEEE/ACM European Design Automation Conference EURO-DAC’93, pages 20–24, Hambourg, September 1993. [ pdf ]
- O. Sentieys, S. Pillement, and D. Chillet. Behavioral IP Specification and Integration Framework for High-Level Design Reuse. In IEEE International Symposium on Quality Electronic Design, ISQED’2002, pages 388 – 393, March 2002. [ pdf ]
- O. Sentieys, D. Chillet, J.P. Diguet, and J.L. Philippe. Memory module selection for high level synthesis. In IEEE Press, VLSI Signal Processing IX, 1996. [ pdf ]
- M. Auguin, M. Belhadj, J. Benzakki, C. Carriere, G. Durrieu, T. Gauthier, M. Israel, P. Le Guernic, M. Lemaitre, E. Martin, P. Quinton, L. Rideau, F. Rousseau, and O. Sentieys. Framework and multi-formalism: The asar project. In Electronic Design Automation Framework, Edited by F.J.Ramming and F.R.Wagner, Chapman Hall, volume 4, pages 91–90, 1995.
- J.L. Philippe, O. Sentieys, J.P. Diguet, and E. Martin. From digital signal processing specifications to layout, pages 307–313. In New techniques in Logic and Architectural Synthesis, Chapman Hall, G. Saucier and A. Mignotte, 1995.
- S. Gailhard, O. Sentieys, N. Julien, and E. Martin. Area/time/power space exploration in module selection for dsp high level synthesis. In PATMOS’97, Louvain la Neuve, September 1997.
- O. Sentieys, E. Martin, and J.L. Philippe. VLSI architectural synthesis for an acoustic echo cancelation application. In IEEE Press, VLSI Signal Processing VI, edited by L. Eggermont and Ed Deprettere, 1993.
- S. Pillement, O. Sentieys, D. Chillet, E. Casseau, P. Coussy, E.Martin, G. Savaton, S. Roux, Design and synthesis of behavioral level virtual components, in 11th IFIP Int. Conference on VLSI and System On Chip, December 2001.
- O. J. Dedou, D. Chillet, and O. Sentieys. Behavioral Synthesis of Aynchronous Systems: a Methodology. In IEEE International Symposium on circuits and systems ISCAS’99, Orlando, USA, may 30 – june 2 1999. [ pdf ]
- O.J. Dedou, D. Chillet, and O. Sentieys. Asynchronous Timing Model for High Level Synthesis for DSP Applications. In European Signal Processing IX: Theories and applications, volume 1, pages 475–478. EUSIPCO-98, September 1998. [ pdf ]
- D. Chillet, O. Sentieys, and M. Corazza. Memory unit design for real time DSP applications. In IEEE Great Lakes Symposium on VLSI GLSV’99, Ann Arbor, Michigan, USA, March 1999.
- J.Ph. Diguet, O. Sentieys, D. Chillet, and J.L. Philippe. VLSI high level synthesis of fast exact least mean square algorithms. In ICASSP’97, 34th IEEE International Conference on Acoustic Speech, and Signal Processing, Munich, Germany, April 1997.
- O. Sentieys, J.P. Diguet, J.L. Philippe, and E. Martin. Hardware module selection for real time pipeline architectures using probabilistic cost estimation. In IEEE ASIC conference, Rochester, USA, September 1996.
- O. Sentieys, J.P. Diguet, and J.L. Philippe. Gaut : a high level synthesis tool dedicated to real time processing application. In University booth, EURO DAC, Brighton, September 1995.
- P. Aubry, M. Auguin, M. Belhadj, J. Benzakki, C. Carriere, G. Durrieu, T. Gauthier, M. Israel, P. Le Guernic, M. Lemaitre, E. Martin, P. Quinton, L. Rideau, F. Rousseau, and O. Sentieys. Framework and multi-formalism: the asar project. In 4eme international IFIP conference on Electronic Design Automation Frameworks, Gramado, Bresil, November 1994.
- M. Auguin, M. Belhadj, J. Benzakki, C. Carriere, G. Durrieu, T. Gauthier, M. Israel, P. Le Guernic, M. Lemaitre, E. Martin, P. Quinton, L. Rideau, F. Rousseau, and O. Sentieys. Towards a multi-formalism framework for architectural synthesis: the asra project. In 3eme international Workshop on hardware – software Codesign Code/Cashe’94, Grenoble, 1994.
- J.P. Diguet, O. Sentieys, E. Martin, and J.L. Philippe. How to specify an algorithm in VLSI architectural synthesis? a vocal coding application. In IEEE Press, VLSI Signal Processing VII, 1994.