PhD

I am always looking for passionate, skilled graduate students in the area of Computer Architecture, Low Power VLSI Design, Approximate Arithmetic. So, if you feel that your talents are exceptional, do not hesitate to contact me.

New PhD Subjects and Available Positions

  • Low-power digital baseband transceiver for wireless network-on-chip architectures (subject, sujet)
  • Predictable and fault-­tolerant multicore architecture (subjectsujet)
  • Sensor-aided Non-Intrusive Appliance Load Monitoring: Detecting Activity of Devices through Low-Cost Wireless Sensors (sujet)
  • Approximate@runtime: Playing with accuracy at run-time for low-power flexible circuits in IoT nodes (subject)

Current PhD students

  • Rafail Psiakis, A Self-Healing Reconfigurable Accelerator Structure for Fault- Tolerant Multi-Cores, Oct. 2015, co-supervised with A. Kritikakou.
  • Van-Dung Pham, Architectural Explorations of 3D Multicores with Optical Network-on-Chip, Dec. 2014, co-supervised with C. Killian and D. Chillet.
  • Benjamin Barrois, Approximate Computing: a New Paradigm for Energy-Efficient Computing Architectures, Oct. 2014.
  • Baptiste Roux, Architectural Exploration of a Low-Power Flexible Radio Embedded on Drones, Oct. 2014, co-supervised with M. Gautier.
  • Rengarajan Ragavan, Ultra-Low Power Reconfigurable Architectures for Computing and Control in Wireless Sensor Networks, Nov. 2013, co-supervised with C. Killian.
  • Xuan-Chien Le, SmartSense: Indirect Monitoring in Self-Powered Wireless Sensor Networks for Smart Grid and Building Automation, Oct. 2013, co-supervised with B. Vrigneau.
  • Gaël Deest, Computing with Errors: Error-Tolerant Machine Code Generation for Unreliable Embedded Hardware, Oct. 2013, supervised by S. Derrien.
  • Florent Berthier, an Ultra Low Power Asynchronous Core for Sensor Networks, Oct. 2013, co-supervised with P. Vivet and E. Beigné from CEA Leti.

Former PhD Students

  • Christophe Huriaux, Enhanced FPGA Architecture and CAD Flow for Efficient Runtime Hardware Reconfiguration, Dec. 2015, co-supervised with A. Courtay. Committee: G. Lemieux (R), L. Torres (R), L. Anghel, P. Millet, R. Tessier.
  • Pramod Udupa, Low Complexity, Parallel Algorithms and Scalable Architectures for Real Time Coherent Optical OFDM Systems, June 2014, co-supervised with L. Bramerie (Foton). Committee: E. Boutillon (R), C. Jego (R), L. Bossuet, E. Pincemin, M. Jezequel. Now Engineer at Signalchip Innovations Pvt. Ltd, Bangalore.
  • Ganda-Stéphane Ouedraogo, Automatic Synthesis of Hardware Accelerators from High-Level Specifications of Physical Layer Waveform for Flexible Radio, Dec. 2014, co-supervised with M. Gautier. Committee: T. Risset (R), R. Pacalet (R), C. Moy, D. Noguet. Now Research Engineer at NestWave, Paris.
  • Matthieu Texier, Dynamic Parallelism Management in Multi-Core Architectures for Mobile Systems, Dec. 2014, co-supervised with R. David and K. Benchehida (CEA). Committee: F. Rousseau (R), A. Pegatoquet (R), J.P. Diguet, H.-P. Charles. Now Engineer Krono-Safe, Saclay, France.
  • Trong Nhan Le, Global Power Manager System for Self-Powered Autonomous Wireless Sensor Node, June 2014, co-supervised with O. Berder and A. Pégatoquet (U. Nice). Committee: J.F. Diouris (R), C.D. Pham (R), M. Magno, C. Bernier, J.P. Diguet. Now PostDoc U. Nice.
  • Amine Didioui, Energy-Aware Transceiver for Energy Harvesting Wireless Sensor Networks, Oct. 2014, co-supervised with C. Bernier (CEA LETI). Committee: D. Dallet (R), F. Mieyeville (R), S. Bourdel, R. Briand, R.M. Sauvage. Now Research Engineer at SEB R&D, Lyon, France.
  • Robin Bonamy, Power Consumption Modeling and Optimisation for Reconfigurable Platform, July 2013, co-supervised with D. Chillet and S. Bilavarn (LEAT, Nice). Committee: M. Renovell (R), C. Piguet (R), E. Senn, C. Jego. Now Research Engineer, CNRS, Nice.
  • Mahtab Alam, Power Aware Adaptive Techniques for Wireless Sensor Networks, 26 Feb. 2013, co-supervised with D. Menard and O. Berder. Committee: E. Popovici (R), T. Risset (R), A. Pegatoquet. Now Research Scientist, Qatar Mobility Innovations Center. Now Research Scientist, Qatar Mobility Innovations Center.
  • Vivek Tovinakere Dwarakanath, Ultra-Low Power Reconfigurable Architectures for Controllers in Wireless Sensor Network Nodes, 12 Feb. 2013, co-supervised with S. Derrien. Committee: P. Girard (R), M. Belleville (R), J.P. Diguet, I. O’Connor. Now a Senior Architect in Nvidia, Bangalore.
  • Vinh Tran, Energy Optimisation of Cooperative Transmissions for Wireless Sensor Networks, Dec. 2012, co-supervised with O. Berder. Committee: J.M. Gorce (R), J.F. Diouris (R), L. Deneire, P. Mary. Now PostDoc, CEA Leti, Grenoble, France.
  • Karthick Parashar, System-level Approach for Implementation and Optimization of Signal Processing Applications into Fixed-Point Architectures, Dec. 2012, co-supervised with D. Menard. Committee: C. Carreras (R), C. Jego (R), F. Catthoor, A. Jerraya. Now Researcher, IMEC, Leuven, Belgique, formerly PostDoc, Imperial College, London, UK.
  • Antoine Eiche, Real-Time Scheduling for Heterogeneous and Reconfigurable Architectures using Neural Network Structures, Sep. 2012, co-supervised with D. Chillet and S. Pillement. Committee: O. Temam (R), Y. Trinquet (R), E. Martin, D. Demigny. Now Engineer, Mandriva, Paris, France.
  • Hai Nam Nguyen, Numerical Accuracy Optimization for Low-Power Embedded Systems, Dec. 2011, co-supervised with D. Menard. Committee: M. Jezequel (R), L. Fesquet (R), C. Moy, F. Horlin, D. Noguet. Now Engineer, Open Web Solutions, Paris, France.
  • Adeel Pasha, System-Level Synthesis of Ultra Low-Power Wireless Sensor Network Node Controllers: A Complete Design-Flow, Dec. 2010, co-supervised with S. Derrien. Committee: C. Piguet (R), F. Petrot (R), C. Belleudy, T. Risset. Now Assistant Professor at LUMS (Lahore Univ. of Management Sciences), School of Science and Engineering, Lahore, Pakistan.
  • Erwan Grace, Memory-Oriented Reconfigurable Embedded Architecture, oct. 2010, co-supervised with D. Chillet and R. David (CEA). Now with Alcatel-Lucent.
  • Tuan Duc Nguyen, Cooperative MIMO Strategies for Energy Constrained Wireless Sensor Networks, may 2009, co-supervised with O. Berder. Committee: JM. Gorce (R), JF. Diouris (R) E. Boutillon (P), M. Dohler. Now Assistant Professor at International University – Vietnam National Univ. – Hochiminh City.
  • Renaud Santoro, High-Rate True Random Number Generators with Guaranteed Quality, dec. 2009, co-supervised with S. Roy (Laval Univ., CA), cotutelle. Now with Alcatel-Lucent. Committee: B. Rouzeyre (R), R. Tessier (R) V. Fischer (P), P. Fortier.
  • Antoine Courtay, Power Consumption of On-Chip Interconnections: High-Level Estimation and Architecture-Level Optimizations, nov. 2008, co-supervised with J. Laurent (LESTER, Lorient). Now Assistant Professor at Univ. Rennes 1 (ENSSAT), formerly a PostDoc at Univ. Nice. Committee: M. Belleville (R), B. Rouzeyre (R) S. Piestrak (P), Y. Leduc.
  • Julien Lallet, Mozaïc: a Generic Platform for Modeling and Design of Dynamically Reconfigurable Architectures, nov. 2008, co-supervised with S. Pillement. Now with Alcatel-Lucent after a PostDoc at the Heinz Nixdorf Institut of Univ. Paderborn. Committee: L. Torres (R), B. Granado (R) S. Piestrak (P), L. Lagadec.
  • Mickael Cartron, Energy Optimization of Wireless Sensor Networks, dec. 2006. Now Researcher at CEA List Saclay. Committee: M. Auguin (R), J.F. Diouris (R), P. Garda.
  • Romuald Rocher, Accuracy and Range Evaluation of Fixed-Point Systems, dec. 2006, co-supervised with D. Menard. Now Assistant Professor at Univ. Rennes 1 (IUT de Lannion). Committee: J.M. Brossier (R), M. Bellanger(R), G. Demoment.

And also…

  • Faten Ben Abdallah, Étude et optimisation de l’interaction processeurs-architectures reconfigurables dynamiquement, 2009. Thèse en cotutelle avec l’ENI de Tunis. Actuellement maître assistant à l’ENISo (Tunisie). Jury: M. Paindavoine (R), R. Bouallegue (R), G. Gogniat.
  • Taofik Saïdi, Architectures pour les communications MIMO avec échantillonnage parallèle et adaptatif, 2008. Thèse en cotutelle avec l’Université Laval, Québec, Canada. Actuellement ingénieur chez Amesys. Jury: JL. Danger (R), JF. Frigon (R), P. Fortier.
  • Imène Benkermi, Système d’exploitation temps réel pour architectures parallèles reconfigurables hétérogènes, 2007. Ingénieur chez Valeo. Jury: B. Granado (R), J.P. Diguet (R), Y. Trinquet.
  • Nicolas Hervé, Méthodologie de conception des architectures reconfigurables en précision finie, 2007. Actuellement en Post-Doc à l’Université de Sao Paulo au Brésil. Jury: B. Rouzeyre (R), T. Risset (R), J.L. Philippe.
  • Ekué Kinvi-Boh, Architectures de systèmes intégrés en logique ternaire}, soutenue en novembre 2006. Actuellement ingénieur dans une société de service. Jury: D. Etiemble (R), S. Piestrak (R), J.D Legat.
  • Stéphane Chevobbe, Unité de commande pour systèmes parallèles : contrôleur basé sur l’implémentation dynamique de réseaux de Pétri, 2005. Actuellement chercheur au CEA Saclay. Jury: M. Auguin (R), A. Mérigot (R), J.D Legat, D. Demigny.
  • Jean-Marc Philippe, Intégration des réseaux sur silicium : optimisation des performances des couches physique et liaison, 2005. Actuellement chercheur au CEA Saclay. Jury: G. Cambon (R), S. Roy (R), J.P. Diguet, C. Gamrat.
  • Raphaël David, Architecture reconfigurable dynamiquement pour applications mobiles, 2003. Actuellement chercheur au CEA Saclay. Jury: G. Cambon (R), D. Demigny (R), T. Collette, D. Lavenier.
  • Raofeng Yu, Estimation de haut niveau du placement et des interconnexions de circuits VLSI submicroniques, 2002. Actuellement ingénieur dans une société chinoise. Jury: A. Mérigot (R), S. Piestrak (R), E. Martin.
  • Alexandre Buisson, Implémentation efficace d’un codeur vidéo hiérarchique granulaire sur une architecture multi-pentium, 2002. Ingénieur chez Nextamp, Rennes. Jury: JM. Chassery (R), R. Prost (R), S. Pateux, P. Sainrat.
  • Daniel Ménard, Méthodologie de compilation d’algorithmes de traitement du signal en précision infinie pour les processeurs en virgule fixe, 2002. Actuellement MCF à l’ENSSAT, Lannion Jury: D. Demigny (R), T. Risset (R), E. Martin, P. Le Guernic.
  • Matthieu Denoual, Estimation au niveau architectural de la consommation des systèmes intégrés dédiés au traitement numérique du signal, 2001. Post-doc au LIMMS à Tokyo (Japon). Actuellement MCF à l’ENSICaen. Jury: B. Rouzeyre (R), C. Piguet (R), E. Martin, D. Lavenier.
  • Joseph Dedou, Synthèse architecturale des systèmes asynchrones, 2000. Ingénieur à Mitsubishi R&D Jury: A. Mérigot (R), S. Piestrak (R), E. Martin, J.D. Legat.
  • Jean-Gabriel Cousin, Méthodologie de conception de coeurs de processeurs spécifiques : mise en  oeuvre sous contraintes, estimation de la consommation, 1999. Actuellement MCF à l’INSA de Rennes. Jury: M. Auguin (R), J.L. Philippe (R), J.P. Calvez, S. Rajopadhye.
  • Daniel Chillet, Méthodologie de conception architecturale des mémoires pour circuits dédiés au traitement du signal temps réel, 1997. Actuellement MCF à l’ENSSAT, Lannion. Jury: F. Catthoor (R), J.P. Calvez (R), E. Martin, J.L. Philippe.
  • Jean-Philippe Diguet, Estimation de complexité et transformations d’algorithmes de traitement du signal pour la conception de circuits VLSI, 1996. Actuellement CR1 CNRS au LESTER, Lorient. Jury: Y. Sorel (R), P. Duhamel (R), M. Arndt.